Liam Patterson

Quad-Core Pipelined Microprocessor

RISC-V, SystemVerilog, and PyMTL

As part of coursework for Cornell University’s Fall 2019 ECE 4750: Computer Architecture course, we built a quad core microprocessor with support for a modified version of the RISC-V ISA. Generally, each core utilizes its own instruction and data cache, with an overall cache and memory network linking each core together and with the main memory of the system.